Semiconductor devices face a number of challenges during the formation of a plurality of device package dies on a wafer. This is particularly the case for chip scale package metal oxide semiconductor field effect transistor (MOSFET) devices, especially vertical conduction power MOSFET devices having gate and source regions on one surface of a semiconductor substrate and a drain region on the opposite surface. Electrical connections are formed on the front surface of a given semiconductor device and electrical connections must additionally be formed on the back surface of the device. In a semiconductor package, electrical connections from both sides of the device must generally be extended to a common plane to allow for post-packaging use of the device. For semiconductor devices such as vertical conduction power MOSFET devices, it is desirable to work towards a smaller land pattern/minimized footprint and a smaller package thickness. This follows the industry trend of miniaturization of electronics, moving towards an optimal true chip scale package. It is similarly desirable to have a smaller electrical resistance, e.g., on resistance Rdson, associated with each semiconductor device package die. This may be accomplished by reducing the thickness of the semiconductor device package die. Since conduction occurs vertically through the semiconductor die, reducing the thickness of the semiconductor die will dramatically reduce the on resistance of the device.
Better thermal dissipation is another desirable feature for semiconductor device package dies, and this can be achieved by using bottom and top exposure. Another desired result is providing greater support to the semiconductor device. Greater stability associated with greater support will also minimize the risk of damaging the semiconductor device chip/substrate. Lastly, it is important that the fabrication of these semiconductor device package dies be accomplished as a wafer level batch process in order to maximize efficiency and minimize the time and costs needed to produce these semiconductor device package dies.
For semiconductor devices with multiple connections on one surface and at least one connection on the opposite surface (e.g., MOSFET device), achieving the desired features discussed above will require novel arrangement in extending connections to a common plane.
It is also generally desirable to have simple, quick, and efficient methods of packaging semiconductor devices.
Typically, semiconductor wafers start out thick in order to provide structural support during wafer handling and the various processes involved in fabricating the semiconductor device. After the front side (device side) processes have been completed, the dies typically undergo a backgrinding process, to remove the back substrate portions. For integrated circuit (IC) chips, the wafer can be made extremely thin because little or no further wafer processing is required, since all the device components are located in the already complete front side of the wafer. However vertical conduction devices such as vertical power MOSFETs require further backside processing after the backside grinding, (e.g. etching, back metal formation, etc.), and so require more mechanical support to avoid wafer damage. Conventional methods have been developed to make ultra thin (e.g., about 2 to 4 mils) wafers/dies for vertical power devices. For perspective, 2 mils is about the diameter of a human hair and much thinner than a piece of paper. A wafer at this thickness or smaller is fragile and easy to damage. However, a thinner wafer can have a lower electrical resistance in vertical semiconductor devices, i.e., devices in which the current flow is vertical, i.e., perpendicular to the wafer surface. Reducing the wafer thickness is an effective way to reduce Rdson. The substrate electrical resistance may be 50% of the total Rdson in low voltage power trench MOSFET devices with a wafer thickness of 8 mils. The use of ultra thin wafers further ensures that the power devices can meet stringent total package thickness requirements. However, the thinner a vertical semiconductor wafer becomes, the higher the risk for damage (e.g. wafer cracking or chipping) during the backside processing and other post-backgrinding processes of the wafer.
FIGS. 1A-1E are cross-sectional diagrams illustrating an example of 3M™ wafer support system for thinning and handling a wafer, such as Si or glass, by a spin coating method. As shown in FIG. 1A, a layer of UV resin or UV-cured liquid 106 is spun on to make a coating on a front surface 107 of a wafer 108 of a starting thickness of about 750 microns. The coated wafer is then turned upside down and is vacuum bonded to a support glass 102 with a Light-To-Heat-Conversion (LTHC) release compound 104 deposited between the support glass 102 and the UV resin coat 106. UV irradiation is applied to cure the resin coating. As shown in FIG. 1B, the wafer 108 is thinned by grinding its back surface 110 with a grinding wheel 112 down to, e.g., 20 microns. The resulting thinned wafer 108 with the attached support glass 102 is again turned upside down and positioned on a dicing tape 114 having dicing frame 116 for holding the wafer as shown in FIG. 1C. Laser irradiation is applied onto the LTHC release 104 in order to remove the support glass 102. As shown in FIG. 1D, the support glass 102 is removed from the UV resin layer 106 and the wafer 108. As shown in FIG. 1E, the UV resin layer 106 is peeled off from the thinned wafer 108. In this conventional method, wafer level thinning and handling can be handled easily and similar to full thickness wafer. However, there are some disadvantages associated with this method. For example, the adhesive 104, resin 106 and other polymeric material may outgas in a vacuum chamber during vacuum processing steps, such as metallization. The steps of de-attaching the handle wafer (support glass 102) may involve risk of wafer breakage. Finally, the total thickness variation (TTV) depends on the accuracy of the handle wafer thickness. This makes the handle wafer more expensive because the handle wafer can only be re-used a limited number of times.
Alternatively, self-supported ring grinding technique could be used to grind a central portion of wafer and leave support ring of unground wafer material at the edge. This technique provides mechanical support without having to use a handle wafer.
U.S. Pat. No. 7,776,746 discloses a method and apparatus for ultra thin wafer backside processing. As shown in FIG. 2, the apparatus 100 comprises an outer ring 110 of generally toroidal configuration that can be formed of any suitably rigid material such as metal or a semiconductor. Outer ring 110 may have any configuration and preferably has a rectangular cross section for facilitating the use of the apparatus with a clamp. The outer ring 110 may be sized to accommodate therewithin a wafer 140. The outer ring 110 may have an outer diameter of 8 inches to accommodate therewithin a 6-inch wafer. A high temperature grinding and/or dicing tape 120 can be affixed or otherwise adhered about the outer ring 110 on a bottom surface 145 thereof. The tape 120 may include a back grinding and/or dicing tape that can resist the temperatures associated with wafer backside processing such as metallization. The outer ring 110 provides a holding mechanism for, and rigid support to, the high temperature tape 120.
U.S. Pat. No. 6,162,702 discloses a self-supported ultra thin silicon wafer process. FIGS. 3A-3B show back side and cross-sectional views of a finished ultra thin silicon wafer indicating with the space between the concentric circumferences the thicker outer rim of the wafer. In this process a mask is used to form a self-supported ring or grid for ultra thin wafer. As shown in FIG. 3B, a silicon wafer 304 has an ultra thin central portion that is supported by a circumferential rim 302 of thicker silicon. The central region is thinned by conventional means using conventional removal apparatus. As an alternative method, the central portion is removed using a photoresist mask or a combination of a photoresist mask and a hard mask.
US patent publication No. 2009/0020854 discloses a process of forming ultra thin wafers having an edge support ring. The process provides an edge support ring having an angled inner wall compatible with spin etching the ultra thin central portion of a wafer after the back grinding process. Following the spin etch process, no drying process is necessary before loading the wafer into the vacuum chamber for back metallization and before the back metallization process. As shown in FIG. 4, which is a schematic diagram showing the flow of spin etch chemicals during a spin etch process, a wafer 80 includes a substantially non-linear angled inner wall 86 extending and curving upwardly from a plane of an ultra thin central portion 81 to a top 88 of an edge support ring 85 formed on a backside 89 thereof. Chemical etch and de-ionized water can be spun from the wafer 80 during the spin etch process as indicated by the arrows. The edge support ring 85 provides the benefits of reduced handling and processing of the wafer 80 during subsequent processing.
The advantages of the above conventional methods are that no other materials brought into vacuum chamber except for the semiconductor wafer itself, so concern over outgassing are reduced. In addition, TTV is better compared to handle wafer approaches and there is lower cost for consumables. Unfortunately, conventional automatic wafer handling systems are not necessarily designed for moving an ultra-thin wafer with support ring and thus may break the fragile ultra-thin portion of the wafer thereby destroying the wafer. Consequently, the wafer cannot be handled as a normal wafer and the standard wafer handling equipment has to be modified to accommodate the special structure with rings.
All of the foregoing prior art is related to thin wafer handling techniques. The assumption in these techniques is that “thin die” handling is not a problem. However, thin die handling could be a significant problem if the thickness of the wafer is reduced further, e.g., down to 1 mil or less, where the thinned wafer is extremely fragile and vulnerable to damage. Use of thinner wafers poses greater risks of breakage during processing and handling at both the wafer level and the die level. Thin wafer handling especially becomes an issue with vertical conducting semiconductors, because backside processing (e.g., metallization) is required on the fragile ultrathin wafer after the back grinding. None of the above approaches may be adequate for wafers this thin.
It is within this context that embodiments of the present invention arise. In addition, the need arises for an effective way to bring connection from the both front and back surfaces of the chip to a single plane for post-packaging use of the device.